1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a method and an apparatus for driving a plasma display panel.
2. Description of the Background Art
A plasma display panel (hereinafter, referred to as a ‘PDP’) is adapted to display an image by light-emitting phosphors with ultraviolet generated during the discharge of a gas such as He+Xe, Ne+Xe or He+Ne+Xe. This PDP can be easily made thin and large, and it can provide greatly increased image quality with the recent development of the relevant technology. Particularly, a three-electrode AC surface discharge type PDP has advantages of lower driving voltage and longer product lifespan as a wall charge is accumulated on a surface in discharging and electrodes are protected from sputtering caused by discharging.
Referring to FIGS. 1 and 2, a three-electrode AC surface discharge type PDP includes scan electrodes Y1 to Yn and a sustain electrode Z which are formed on the bottom surface of an upper substrate 10, and address electrodes X1 to Xm formed on a lower substrate 18.
Discharge cells of the PDP are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z and the address electrodes X1 to Xm.
Each of the scan electrodes Y1 to Yn and the sustain electrode Z include a transparent electrode 12, and a metal bus electrode 11 which has a line width smaller than that of the transparent electrode 12, and is disposed at one side edge of the transparent electrode. The transparent electrode 12, which is generally made of ITO (indium tin oxide), is formed on the bottom surface of the upper substrate 10. The metal bus electrode 11, which is generally made of metal, is formed on the transparent electrode 12, and serves to reduce a voltage drop caused by the transparent electrode 12 having high resistance. On the bottom surface of the upper substrate 10 in which the scan electrodes Y1 to Yn and the sustain electrode Z are placed parallel with each other is laminated an upper dielectric layer 13 and a protective layer 14. On the upper dielectric layer 13 are accumulated wall charges generated during plasma discharging. The protective layer 14 is adapted to protect the electrodes Y1 to Yn and Z, and the upper dielectric layer 13 from sputtering generated during plasma discharge, and improve efficiency of secondary electron emission. As the protective layer 14, magnesium oxide (MgO) is generally used.
The address electrodes X1 to Xm are formed on the lower substrate 18 in the direction in which they intersect the scan electrode Y1 to Yn and the sustain electrode Z. A lower dielectric layer 17 and a barrier rib 15 are formed on the lower substrate 18. A phosphor layer 16 is formed on the lower dielectric layer 17 and the barrier rib 15. The barrier rib 15 is formed in parallel with the address electrodes X1 to Xm to physically divide the discharge cells, thus precluding electrical and optical interference among neighboring discharge cells 1. The phosphor layer 16 is excited with an ultraviolet generated during the plasma discharging to generate any one visible light of red, green and blue lights.
Inert mixed gases such He+Xe, Ne+Xe and He+Ne+Xe are injected into the discharge spaces of the discharge cells defined between the upper substrate 10 and the barrier ribs 15 as well as between the lower substrate 18 and the barrier rib 15.
This three-electrode AC surface discharge type PDP is driven with one frame being divided into a plurality of sub-fields having a different frequency of emission in order to implement a gray scale of an image and is driven. If it is desired to display an image with 256 gray scales, a frame period (16.67 ms) corresponding to 1/60 seconds is divided into eight sub-fields SF1 to SF8, as shown in FIG. 3. Each of the sub-fields SF1 to SF8 includes a reset period for initializing the discharge cells 1, an address period for selecting the discharge cells, and a sustain period for implementing a gray scale depending on the frequency of discharging. The reset period and the address period of each of the sub-fields SF1 to SF8 are the same every sub-field, whereas the sustain period and the frequency of its discharging number are increased in the ratio of 2n (where, n=0, 1, 2, 3, 4, 5, 6, 7) in each sub-field.
FIG. 4 shows a driving waveform of a PDP.
Referring to FIG. 4, in a set-up period SU of a reset period, a ramp-up waveform Ramp-up is simultaneously applied to all the scan electrodes Y and at the same time 0V is applied to the sustain electrode Z and the address electrode X. A setup discharge occurs as a weak discharge between the scan electrode Y and the address electrode X as well as between the scan electrode Y and the sustain electrode Z within cells of the entire screen due to the ramp-up waveform Ramp-up. Due to the setup discharge, wall charges of the positive polarity (+) are accumulated on the address electrode X and the sustain electrode Z and wall charges of the negative polarity (−) are accumulated on the scan electrode Y.
In a set-down period SD of the reset period, a ramp-down waveform Ramp-dn whose voltage starts falling approximately from a sustain voltage Vs to the ground voltage GND or 0V is supplied to the scan electrodes Y at the same time. While the ramp-down waveform Ramp-dn is supplied to the scan electrodes Y, the sustain voltage Vs of the positive polarity is supplied to the sustain electrode Z and 0V is supplied to the address electrode X.
As such, if the ramp-down waveform Ramp-dn is supplied, a set-down discharge occurs as a weak discharge between the scan electrode Y and the sustain electrode Z as well as between the scan electrode Y and the address electrode X. Excessive wall charges that are not required for an address discharge, among the wall charges formed during the setup discharge are erased by means of the set-down discharge. Variation in the wall charges during the reset period will now be described. It was found that variation in the wall charges on the address electrode X rarely occurs, and the wall charges of the negative polarity (−) on the scan electrode Y that was formed during the setup discharge are partially erased by the set-down discharge. On the contrary, the wall charges of the positive polarity are formed on the sustain electrode Z during the setup discharge, but the wall charges of the negative polarity are accumulated on the sustain electrode Z as the wall charges of the negative polarity are accumulated thereon as much as the reduction amount of the wall charges of the negative polarity on the scan electrode Y.
In an address period, a scan pulse scan of the negative polarity is sequentially applied to the scan electrodes Y, and simultaneously a data pulse data of the positive polarity is supplied to the address electrodes X in synchronism with the scan pulse scan. As a voltage difference between the scan pulse scan and the data pulse data and a wall voltage generated in the reset period are added, an address discharge occurs in on-cells to which the data pulse data is supplied. Wall charges are formed in on-cells selected by the address discharge to the extent of generating a discharge when the sustain voltage Vs is applied. During the address period, a DC voltage Zdc of the positive polarity is applied to the sustain electrode Z.
In a sustain period, the sustain pulse sus is alternately applied to the scan electrodes Y and the sustain electrodes Z. In the on-cells selected by the address discharge, as the wall voltage and the sustain pulse sus within the cells are added, a sustain discharge, i.e., a display discharge occurs between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is supplied.
The sustain discharge is followed by an erase period. In the erase period, an erase ramp waveform ramp-ers whose pulse width and voltage level are small is supplied to the sustain electrode Z, so that the wall charges remaining in the cells of the entire screen are erased.
As in the driving waveform shown in FIG. 4, if the voltage of the ramp-down waveform Ramp-dn falls down to only 0V, an erase operation wherein wall charges on the upper substrate that are required for the address discharge uniformly remain in all the discharge cells cannot be properly performed. For this reason, there was proposed a method wherein a voltage of the ramp-down waveform Ramp-dn is lowered to a voltage of the negative polarity, so that an erase discharge can be performed sufficiently and uniformly in all the discharge cells 1 as shown in FIG. 5.
As the PDP makes it difficult to control the wall charges of the reset period and has a high voltage of the ramp waveform, a setup discharge and set-down discharge of the reset period occur relatively high. Thus there is problem that contrast characteristic is poor. In a conventional method for driving a PDP, a ramp waveform for initializing the PDP has to be set differently depending on a cell condition and a driving condition of each PDP. For example, a slope, a voltage, etc. have to be set differently. Therefore, if a new PDP having a different cell condition and driving condition is developed, a voltage of a ramp waveform, a slope and the like have to be decided through lots of experiences.
Resolution of the PDP has been increased and the image quality of the PDP has been significantly improved. If sub-fields are added in order to increase resolution or the image quality as such, an address driving time is lengthened, which makes a driving time run short. Such shortage of the driving time can be solved through a dual scan method wherein two lines in the PDP are scanned at the same time. In this case, however, there is a problem that a drive integrated circuit has to be added due to the dual scan method. Accordingly, research on a method circuit has recently been made actively in which the image quality can be improved while driving a PDP in a single scan mode without using additional drive integrated.
Furthermore, for higher efficiency of the PDP, a method has recently been proposed in which Xe content is increased by over 10% in a discharge gas. If Xe content is increased as such, the ramp voltage in the reset period is increased and discharge delay, particularly an address jitter value is increased, which results in an increase in a scan time and an address period. It is thus impossible to drive a PDP in a single scan, a driving margin becomes narrow and a sustain operation becomes unstable.